All electronic display technologies are composed of a large array of display picture elements, called pixels arranged in a two-dimensional matrix. Color is added to these displays by subdividing each pixel element into three-color subpixels. The electronic display technologies can be further divided into a category known as flat-panel displays. The basic structure of a flat-panel display comprises two glass plates with a conductor pattern of electrodes on the inner surfaces of each plate with additional structure to separate the plates or create a channel. The conductors are configured in a x-y matrix with horizontal and vertical electrodes deposited at right angles from each other to allow for matrix addressing. Examples of flat-panel displays include plasma displays, plasma addressed liquid crystal (PALC) displays, field emission displays (FED), and the like.
Plasma display panels (PDP) have been around for about 30 years, however they have not seen widespread commercial use. The main reasons are the short lifetime, low efficiency, and cost of the color plasma displays. Most of the performance issues were solved with the invention of the three electrode surface discharge AC plasma display (G. W. Dick, “Three-Electrode per PEL AC Plasma Display Panel”, 1985 International Display Research Conf., pp. 45-50; U.S. Pat. Nos. 4,554,537, 4,728,864, 4,833,463, 5,086,297, 5,661,500, and 5,674,553). The new three electrode surface discharge structure advances many technical attributes of the display, but its complex manufacturing process and detailed structure makes manufacturing complicated and costly.
Currently, plasma display structures are built up layer by layer on specialty glass substrates using many complex processing steps. FIG. 1 illustrates the basic structure of a surface discharge AC plasma display made using standard technology. The PDP can be broken down into two parts: top plate 10 and bottom plate 20. The top plate 10 has rows of paired electrodes referred to as the sustain electrodes 11a, 11b. The sustain electrodes are composed of wide transparent indium tin oxide (ITO) electrodes 12 and narrow Cr/Cu/Cr bus electrodes 13. These electrodes are formed using sputtering and multi-layer photolithography. The sustain electrodes 11 are covered with a thick (25 μm) dielectric layer 14 so that they are not exposed to the plasma. Silk-screening a high dielectric paste over the surface of the top plate and consolidating it in a high temperature process step forms this dielectric layer 14. A magnesium oxide layer (MgO) 15 is deposited by electron-beam evaporation over the dielectric layer to enhance secondary emission of electrons and improve display efficiency. The bottom plate 20 has columns of address electrodes 21 formed by silk-screening silver paste and firing the paste in a high temperature process step. Barrier ribs 22 are then formed between the address electrodes 21. These ribs 22, typically 50 μm wide and 120 μm high, are formed using either a greater than ten layer multiple silk-screening process or a sandblasting process. In the sandblasting method, barrier rib paste is blade coated on the glass substrate. A photoresist film laminated on the paste is patterned by photolithography. The rib structure is formed by sandblasting the rib paste between the exposed pattern, followed by removal of the photoresist layer and a high temperature consolidation of the barrier rib 22. Alternating red 23R, green 23G, and blue 23B phosphors are silk-screened into the channels between the barrier ribs to provide color for the display. After silk-screening the phosphors 23, the bottom plate is sandblasted to remove excess phosphor in the channels. The top and bottom plates are frit sealed together and the panel is evacuated and backfilled with a gas mixture containing xenon.
The basic operation of the display requires a plasma discharge where the ionized xenon generates ultraviolet (UV) radiation. This UV light is absorbed by the phosphor and converted into visible light. To address a pixel in the display, an AC voltage is applied across the sustain electrodes 11 which is large enough to sustain a plasma, but not large enough to ignite one. A plasma is a lot like a transistor, as the voltage is increased nothing happens until a specific voltage is reached where it turns on. Then an additional short voltage pulse is applied to the address electrode 21, which adds to the sustain voltage and ignites the plasma by adding to the total local electric field, thereby breaking down the gas into a plasma. Once the plasma is formed, electrons are pulled out of the plasma and deposited on the MgO layer 15. These electrons are used to ignite the plasma in the next phase of the AC sustain electrodes. To turn the pixel off, an opposite voltage must be applied to the address electrode 21 to drain the electrons from the MgO layer 15, thereby leaving no priming charge to ignite the plasma in the next AC voltage cycle on the sustain electrodes. Using these priming electrons, each pixel can be systematically turned on or off. To achieve gray levels in a plasma display, each video frame is divided into 8 bits (256 levels) and, depending on the specific gray level, the pixels are turned on during these times.
There are presently three address modes of operation for a standard AC plasma display: (1) erase address (U.S. Pat. No. 5,446,344), (2) write address (U.S. Pat. No. 5,661,500), and (3) ramped voltage address (U.S. Pat. No. 5,745,086). The prior art wave forms for the matrix erase address waveform is shown in FIG. 2. In the initial address cycle CA in the line display period T a discharge sustain pulse PS is applied to the display electrode 11a and simultaneously a writing pulse in applied to the display electrode 11b. In FIG. 2, the inclined line in the discharge sustain pulse PS indicates that it is selectively applied to lines. By this operation, all surface discharge cells are made to be in a written state.
After the discharge sustain pulses PS are alternately applied to the display electrodes 11a and 11b to stabilize the written states, and at an end stage of the address cycle CA, an erase pulse PD is applied to the display electrode 11b and a surface discharge occurs.
The erase pulse PD is short in pulse width, 1 μs to 2 μs. As a result, wall charges on a line as a unit are lost by the discharge caused by the erase pulse PD. However, by taking a timing with the erase pulse PD, a positive electric field control pulse PA having a wave height Va is applied to address electrodes 21 corresponding to unit luminescent pixel elements to be illuminated in the line.
In the unit luminescent pixel elements where the electric field control pulse PA is applied, the electric field due to the erase pulse PD is neutralized so that the surface discharge for erase is prevented and the wall charges necessary for display remain. More specifically, addressing is performed by a selective erase in which the written states of the surface discharge cells to be illuminated are kept.
In the display period CH following the address cycle CA, the discharge sustain pulse PS is alternately applied to the display electrodes 11a and 11b to illuminate the phosphor layers 23. The display of an image is established by repeating the above operation for all line display periods.
The prior art waveforms for the matrix write address waveform is shown in FIG. 3. At the initial stage of the address cycle CA, a writing pulse PW is applied to the display electrode 11a at the same time a sustain pulse is applied to display electrode 11b so as to make the potential thereof large enough to place each pixel element in the line in a write state. The write pulse PW is followed by two sustain pulses PS to condition the plasma cells. A narrow relative pulse of width t1 is then applied to each pixel element in the line to erase the wall charge. The narrow pulse is obtained by applying a voltage Vs on the sustain electrode 11a a time t1 before a voltage Vs is applied to sustain electrode 11b. In the display line, a discharge sustain pulse PS is selectively applied to the display electrode 11b and a selective discharge pulse PA is selectively applied to the address electrodes 21 corresponding to the unit luminescent pixel elements to be illuminated in the line depending on the image. By this procedure, opposite discharges between the address electrodes 21 and the display electrode 11b or selective discharges occur, so that the surface discharge cells corresponding to the unit luminescent pixel elements to be illuminated are placed into write states and the addressing finishes.
In the display period CH following the address cycle CA, the discharge sustain pulse PS is alternately applied to the display electrodes 11a and 11b to illuminate the phosphor layers 23. The display of an image is established by repeating the above operation for all line display periods.
The prior art wave forms for the matrix ramped voltage address waveform is shown in FIG. 4. During the setup period a voltage ramp PE is applied to the sustain electrode 11b which acts to erase any pixel sites which are in the ON state. After the initial erase a slowly rising ramp potential Vr is applied to the sustain electrode 11a then raised potential is applied to sustain electrode 11b and a falling potential Vf is applied to the sustain electrode 11a. The rising and falling voltages produces a controlled discharge causing the establishment of standardized wall potentials at each of the pixel sites along the sustain line. During the succeeding address pulse period, address data pulses PA are applied to selected column address lines 21 while sustain lines 11b are scanned PSc. This action causes selective setting of the wall charge states at pixel sites along a row in accordance with applied data pulses.
Thereafter, during the following sustain period an initial longer sustain pulse PSL is applied to the sustain electrode 11a to assure proper priming of the pixels in the written state. The remaining sustaining period is composed of discharge sustain pulses PS alternately applied to the display electrodes 11a and 11b to illuminate the phosphor layers 23. The display of an image is established by repeating the above operation for all line display periods.
A number of methods have been proposed to create the structure in a plasma display, such as thin and thick film processing, photolithography, silk screening, sand blasting, and embossing. However, none of the structure forming techniques provides as many advantages as that of using fibers. Small hollow tubes were first used to create structure in a panel by W. Mayer, “Tubular AC Plasma Panels,” 1972 IEEE Conf. Display Devices, Conf. Rec., New York, pp. 15-18, and R. Storm, “32-Inch Graphic Plasma Display Module,” 1974 SID Int. Symposium, San Diego, pp. 122-123, and included in U.S. Pat. Nos. 3,964,050 and 4,027,188. These early applications where focused on using an array of gas filled hollow tubes to produce the rib structure in a PDP. In addition, this work focused on adding the electrode structure to the glass plates that sandwiched the gas filled hollow tubes. Since this early investigation no further work was published on further developing a fiber or tube technology until that published by C. Moore and R. Schaeffler, “Fiber Plasma Display”, SID '97 Digest, pp. 1055-1058.
The present invention is also directed to PALC displays and FEDs. Tektronix, Inc., has disclosed and demonstrate the use of plasma channels to address a liquid crystal display. For example, U.S. Pat. Nos. 4,896,149, 5,036,317, 5,077,553, 5,272,472, 5,313,423, the specifications of which are all hereby incorporated by reference, disclose such structures. The only public knowledge of fibers for PALC displays was published by D. M. Trotter, C. B. Moore, and V. A. Bhagavatula, “PALC Displays Made from Electroded Glass Fiber Arrays”, SID '97 Digest, pp. 379-382. No known publications exist for using fibers for FEDs.
The PALC display, illustrated in FIG. 5, relies on the highly non-linear electrical behavior of a relatively low pressure (10-100 Torr) gas, usually He, confined in many parallel channels. A pair of parallel electrodes 36 are deposited in each of the channels 35, and a very thin glass microsheet 33 forms the top of the channels. Channels 35 are defined by ribs 34, which are typically formed by screen printing or sand blasting. A liquid crystal layer 32 on top of the microsheet 33 is the optically active portion of the display. A cover sheet 30 with transparent conducting electrodes 31 running perpendicular to the plasma channels 35 lies on top of the liquid crystal 32. Conventional polarizers, color filters, and backlights, like those found in other liquid crystal displays, are also commonly used.
Because there is no ground plane, when voltages are applied to the transparent electrodes 31, the voltages are divided among the liquid crystal 32, the microsheet 33, the plasma channel 35, and any other insulators intervening between the transparent electrode 31 and whatever becomes the virtual ground. As a practical matter, this means that if there is no plasma in the plasma channel 35, the voltage drop across the liquid crystal 32 will be negligible, and the pixels defined by the crossings of the transparent electrodes 31 and the plasma channels 35 will not switch. If, however, a voltage difference sufficient to ionize the gas is first applied between the pair of electrodes 36 in a plasma channel 35, a plasma forms in the plasma channel 35 so that it becomes conducting, and constitutes a ground plane. Consequently, for pixels atop this channel, the voltages will be divided between the liquid crystal 32 and the microsheet 33 only. This places a substantial voltage across the liquid crystal 32 and causes the pixel to switch; therefore, igniting a plasma in the channel causes the row above the channel to be selected. Because the gas in the channels is non-conducting, the rows are extremely well isolated from the column voltages unless selected. This high nonlinearity allows very large numbers of rows to be addressed without loss of contrast.